This invention relates to semicustom integrated circuit chips; and more particularly, it relates to ways and means for improving the density with which logic cells are integrated into such chips.
Basically, in a semicustom integrated circuit chip, a plurality of logic cells are arranged in rows which are spaced apart from one another to form channels for interconnecting the cells. Typically, the number of cells per row and the number of rows per chip varies between 20 and 200. Each of the cells is selected from a cell library which contains many different cell types, each of which performs a different logic function. For example, one cell may be a two input NAND gate; another cell may be a four input NOR gate; another cell may be a flip-flop; etc. These cells are selectively interconnected by one set of conductors which lie in the channels parallel to the rows, and another set of conductors which overlie the cells and run perpendicular to the channels.
Each of the cells of the prior art occupies a rectangular shaped surface area of the chip; and the perimeter of this rectangle is formed by the cell's sidewalls which penetrate the chip and lie perpendicular to its surface. These sidewalls define a space in the chip which contains all the transistors and their connections within the cell.
A recent article which illustrates some CMOS logic cells of the above type, as well as their arrangement in spaced apart rows, is "A Spatial Reasoning Approach to Cell Layout Generation" by Mark Alexander, Proceedings of the IEEE 1986 Custom Integrated Circuits Conference (CICC) at page 359. Another recent article which illustrates some bipolar logic cells of the above type is "A Sub 10 ns Low Power Bipolar 16.times.16 Bit Multiplier" by Bruce E. Miller and Robert F. Owen, Proceedings of the IEEE 1986 Custom Integrated Circuits Conference (CICC), at page 99.
In designing a logic cell, one of the most important considerations is to physically lay out the various transistors and their interconnections within the cell such that a minimal amount of chip space is occupied. This is because system designers are always trying to get more and more logic cells on a chip. Consequently, an enormous amount of effort is made by semicustom chip manufacturers to reduce the size of the cells in their cell library.
One way to reduce the size of a logic cell is to use smaller dimensions for the transistors and interconnections which occur within the cell. However, the amount by which the size of a logic cell can be reduced by this approach is reaching a point of diminishing returns. This is because the photolithographic processes by which transistors and their interconnections are patterned are already very refined and are being pressed to their limits.
Accordingly, a primary object of the invention is to provide an entirely different means by which cell size can be decreased dramatically without further pushing the limits of today's lithographic technology.